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These requirements are generally met with a mix of capacitors and careful layout. These should be selected based upon rDS ONgate supply requirements, and thermal management requirements. When attempting to restart a faulted regulator, the ISL will follow the preset start up sequencing.

Careful component layout and printed circuit board design minimizes these voltage spikes. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes.

Shoot-Through Protection A shoot-through condition occurs when both the upper and lower MOSFETs are turned on simultaneously, effectively shorting the input voltage to ground. The lower switch realizes most of the switching losses when the converter is sinking current see the equations below.

Some capacitor series available from reputable manufacturers are surge current tested. Phase margin is the difference between the closed loop phase at f0dB and degrees. L minus L1 to be equal to or greater than 0.

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The minimum value for CSS can be found through the following equation: N is the number of terminals. This transition is represented on Figure 1 at time t If a regulator is already in regulation, then it will not be affected by the start up sequencing. The FB pin is also monitored for under and over-voltage events.


Glitch-free Transitions During State Changes? The filtering requirements are a function of the switching frequency and the datasehet current. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling.

The maximum rDS ON at the highest junction temperature. The response time to a transient is different for the application of load and the removal of load. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. This allows the ISL to attempt at least one full soft-start sequence to restart the faulted regulators. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress.

This pin is also monitored by daatasheet adaptive shootthrough att9173 circuitry to determine when the upper MOSFET has turned off.

This method allows the VDDQ regulator to both source and sink current. It is typically connected to the 5V standby rail of an ATX power supply. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors.

To insure that both upper and lower pass transistors dissipate the same power, tie this pin to the VGMCH output rail. Graphics cards – GPU and memory supplies?


At917 ground currents are conducted directly through the exposed paddle of the QFN package which must be electrically connected to the ground plane through a path as low in inductance as possible. This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain.

OCP on the Switching Regulator? The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency f0dB and adequate phase margin.

Accordingly, the reader is cautioned to verify that data datasjeet are current before placing orders. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. This method provides a rapid and controlled output voltage rise. The power dissipation includes two loss components; conduction loss and switching loss.

This enables the ATX, which brings up the 12V rail.

AT9173 Datasheet

With a properly selected divider, VDDQ can be set to any voltage between the power rail reduced by converter losses and the 0. If the Fault Reset Counter reaches a count of before another fault occurs, then the Fault Counter is cleared to 0. I x ESR If the output voltage desired is 0.